1. Field of the Invention
The invention relates to sample-and-hold circuit for analog electrical signals.
One example of an application for which the present invention is particularly suited is the processing of analog electrical signals derived from photosensitive sensors of the charge-transfer type, or other charge-transfer devices.
2. Discussion of the Background
Although the invention applies in other cases, the example of signals derived from charge-transfer photosensitive sensors will be given.
The constraints in processing these signals are speed and precision of measurement of the signals from these sensors.
The signals are presented in the form of successive voltage square waves separated by a plateaus at a reference voltage level. This corresponds, in fact, to the fact that the signals result from the conversion of packets of photosensitive charges transported by shift registers. The voltage level of one square wave corresponds to a quantity of charges which represents the illumination of a point. The voltage level of a following square wave represents the illumination of the following point. The voltage level of the plateau which separates them corresponds to a black level.
A black level may vary slowly in the course of an analysis of an image, but it is always necessary for the useful signal level of the square waves to be referenced with respect to this black level.
In order to be able to effect processing of the received image point by point, it proves to be necessary to sample and hold the signal level of each square wave for as long a time as possible. That is to say, in practice, during the whole period separating one square wave from the next one. In fact, in order to rapidly process numerous points, it is necessary for them to succeed each other at a high rate, and thus a very short time is available for processing each signal. The processing is, for example, analog-digital conversion.
Hence the signal processing constraints are, on the one hand, the sampling and the holding of the signal over one complete period, and, on the other hand, the establishing of a fixed reference voltage level of the sampled-and-held output signal, knowing that the reference level of the input signal can vary. The other constraints are speed of processing and precision.
FIG. 1 represents, by way of example, the input signal S1 in the form of square waves with the reference plateaus (level Vr1 susceptible to drifting in the course of time) and the useful signal square waves V1, the useful signal value being the difference V1-Vr1 between the level of the square wave and the level of the plateau just before or just after. FIG. 1 also represents the desired output signal S2, namely a signal which is sampled and held during a time interval equal to that which separates two successive square waves of the input signal. The signal S2 is a succession of staircase steps of variable levels V2 which are referenced with respect to a fixed reference voltage V0. Each step level V2 taken with respect to this reference level represents the useful signal level V1 taken with respect to the plateau Vr1. It is assumed, for simplicity's sake, that the sampler which establishes S2 has unity gain.
The conventional solutions used to produce this sampling are the following: the signal input can be applied to one input of a differential amplifier, and applied also to another input of the amplifier, but with a delay corresponding to one input signal half-period (delay produced by a delay line). In this way, one of the inputs receives a useful signal level V1 while the other receives the immediately preceding or following plateau level Vr1. The output of the amplifier is applied to a sample-and-hold device whose reference is the voltage V0. The sample-and-hold device maintains a level V2-V0 which is equal to V1-Vr1 from one sampling instant up to the following sampling.
This circuit operates only on condition that the square waves have very good frequency constancy, so that the delay introduced by the delay line corresponds well to one half-period of the input square waves. If the frequency is changed, it is necessary to change delay lines. Moreover, the differential amplifier is relatively tricky to produce as it has to possess very good common-mode rejection at the frequency of the signal. Otherwise the drift in the reference plateaux of the input signal is not eliminated. A good common-mode rejection is difficult to obtain if it is necessary to work at high frequency.
Another solution uses two sample-and-hold devices receiving the input signal in parallel, one of them sampled during the reference plateaus and the other during the square waves corresponding to the useful signal. A differential amplifier forms the difference between the two sampled-and-held levels and references this difference with respect to a reference level V0. Here again, the amplifier has to possess good common-mode rejection. Moreover the circuit necessitates two sample-and-hold devices, which is more expensive.
A solution using a single sample-and-hold device has been envisaged. It comprises, on the one hand, a sample-and-hold device and, on the other hand, a reference level periodic locking loop at the input of the sample-and-hold device.
The circuit is represented in FIG. 2. The input of the circuit is applied through a capacitor C1 to the input of a basic sample-and-hold device EB1. The output of the sample-and-hold device EB1 constitutes the output S2 of the circuit. At the input and at the output of the sample-and-hold device EB1 are represented buffer amplifiers B1 and B2 respectively, which have a function only of impedance matching in order to avoid charging the capacitors of the circuit by over-heavy currents. However, the sample-and-hold device proper is constituted diagrammatically by a switch followed by a capacitor. The switch permits, when it is closed during a sampling instant, charging the capacitor to the voltage level applied at the input of the sampler. Sampling takes place during the useful signal square waves.
A reference plateau level locking loop is provided. It is represented symbolically in FIG. 2. It comprises a differential amplifier AD1 one input of which is linked to a reference voltage V0; another input is linked to the output of the amplifier; this output is linked, by means of a switch K1, to the input of the sample-and-hold device EB1 (either before or after B1). The switch is closed periodically by a locking signal Sv (which is sent out during the reference plateaus of the input signal and not during the useful square waves).
The circuit operates in the following manner: the locking signal establishes, by looping of the amplifier AD1, the reference voltage level V0 on the input of the sampler. As the locking signal Sv is applied when the input signal is at its plateau Vr1, the capacitor C1 charges to the voltage V0-Vr1.
At the end of the locking signal, the capacitor C1 keeps this charge, the locking loop being disconnected (opening of K1) from the input of the sample-and-hold device. The input signal applied next to the sample-and-hold device is then the useful signal V1 to which it is necessary to add the voltage due to the charge of the capacitor. The signal applied to the sample-and-hold device is therefore V1-Vr1+V0. This is a signal representing the useful level of the square wave with respect to the plateau, but referenced with respect to V0.
It is this level which is sampled in the capacitor C2 of the sample-and-hold device EB1 and which is next kept in memory until the following sampling. The capacitor C2 has one reference end connected, for example, to a zero-potential earth. The following sampling will be preceded by a new locking step of the input plateau with respect to the reference voltage V0.
In other words, if the useful signal is equal to the reference plateau, whatever the level of the reference plateau since the latter can vary, the sampled signal will be equal to V0. If the useful signal is different from the reference level, the difference will be added to V0 in the sampled signal.
The advantage is that it is not necessary to produce a differential amplifier with enhanced characteristics. In fact, there is no common-mode-rejection problem since this amplifier receives only one error signal.
Another advantage is that the output signal can be referenced with respect to a non-nil voltage V0 (that is to say not equal to the voltage with respect to which the capacitor C2 of the sample-and-hold device is charged). In this case, for example, the reference level V0 can be chosen as a function of the zero of the analog-digital converter which will often be found downstream from the sampling circuit.
One difficulty in a practical embodiment of the diagram of FIG. 2 results from the fact that the sample-and-hold device EB1 itself risks introducing a voltage shift, due especially to the junctions of the transistors of which it is comprised (for example in the case of embodiments in bipolar technology). In order to avoid this, it would be possible to provide for the looped-back output of the differential amplifier (and the corresponding input) to be linked to the output of the sample-and-hold device EB1 and not to its input. During the locking signal, the input capacitor C1 then charges to a value such that the output is actually V0 during the plateau. However, this requires supplementary sampling to be provided during the input reference plateau, in order to be able to effect the level locking during this plateau. On the contrary, in fact, it is desirable for the useful signal to be held for as long as possible, that is to say for it to occupy, if possible, the whole duration available between two useful signal square waves.